MSS Memory Map

The overall PolarFire SoC memory map consists of the following:

CPU Core Complex address space, see Table 1.
Peripherals address space, see PolarFire SoC Device Register Map.
Memory address space, see Table 2.

Table 1. CPU Core Complex Address Space
Start Address	End Address	Attributes	Description
0x0000_0000	0x0000_00FF	—	Reserved
0x0000_0100	0x0000_0FFF	RWX	Debug
0x0000_1000	0x00FF_FFFF	—	Reserved
0x0100_0000	0x0100_1FFF	RWXA	E51 DTIM
0x0100_2000	0x016F_FFFF	—	Reserved
0x0170_0000	0x0170_0FFF	RW	Bus Error Unit 0
0x0170_1000	0x0170_1FFF	RW	Bus Error Unit 1
0x0170_2000	0x0170_2FFF	RW	Bus Error Unit 2
0x0170_3000	0x0170_3FFF	RW	Bus Error Unit 3
0x0170_4000	0x0170_4FFF	RW	Bus Error Unit 4
0x0170_5000	0x017F_FFFF	—	Reserved
0x0180_0000	0x0180_1FFF	RWXA	E51 Hart 0 ITIM
0x0180_2000	0x0180_7FFF	—	Reserved
0x0180_8000	0X0180_EFFF	RWXA	U54 Hart 1 ITIM
0x0180_F000	0x0180_FFFF	—	Reserved
0x0181_0000	0x0181_6FFF	RWXA	U54 Hart 2 ITIM
0x0181_7000	0x0181_7FFF	—	Reserved
0x0181_8000	0X0181_EFFF	RWXA	U54 Hart 3 ITIM
0x0181_F000	0x0181_FFFF	—	Reserved
0x0182_0000	0x0182_6FFF	RWXA	U54 Hart 4 ITIM
0x0182_7000	0x01FF_FFFF	—	Reserved
0x0200_0000	0x0200_FFFF	RW	CLINT
0x0201_0000	0x0201_0FFF	RW	Cache Controller
0x0201_1000	0x0201_FFFF	—	Reserved
0x0202_0000	0x0202_0FFF	RW	WCB
0x0202_1000	0x02FF_FFFF	—	Reserved
0x0300_0000	0x030F_FFFF	RW	DMA Controller
0x0310_0000	0x07FF_FFFF	—	Reserved
0x0800_0000	0x081F_FFFF	RWX	L2-LIM
0x0820_0000	0x09FF_FFFF	—	Reserved
0x0A00_0000	0x0BFF_FFFF	RWXC	L2 Zero Device
0x0C00_0000	0x0FFF_FFFF	RW	PLIC
0x1000_0000	0x1FFF_FFFF	—	Reserved

The address range 0x2000_0000 - 0x27FF_FFFF includes the default base addresses (LOW) of low-speed peripherals and base addresses of high-speed peripherals. The address range 0x2800_0000 - 0x2812_6FFF, includes the alternate base addresses (HIGH) of low-speed peripherals. For more information, see PolarFire SoC Device Register Map. The low-speed peripherals can be accessed using the two address ranges (HIGH or LOW) in the memory map. This ensures efficient use of the PMP registers to isolate two AMP contexts.

PolarFire SoC Device Register Map is an easy-to-use web page, which lists and describes the PolarFire SoC memory map. To view the overall PolarFire SoC memory map, follow these steps:

1.Download and unzip the register map folder.
2.Using a browser, open the pfsoc_regmap.htm file from <$download_folder>\Register Map\PF_SoC_RegMap_Vx_x.
3.Select MMUART0_LO to view the subsequent register descriptions and details.
4.Similarly, select the required block to view its subsequent register descriptions and details.

Table 2. Memory Address Space
Start Address	End Address	Attributes	Description
0x3000_0000	0x3FFF_FFFF	RWX	IOSCB-DATA CPU Core Complex - D0 (AXI Switch Master Port M10)
0x3708_0000	0x3708_0FFF	RWX	IOSCB-CONFIGURATION
0x4000_0000	0x5FFF_FFFF	RWX	FIC3 - 512 MB CPU Core Complex - D0 (AXI Switch Master Port M10)
0x6000_0000	0x7FFF_FFFF	RWX	FIC0 - 512 MB CPU Core Complex - F0 (AXI Switch Master Port M12)
0x8000_0000	0xBFFF_FFFF	RWXC	DDR Cached Access - 1 GB
0xC000_0000	0xCFFF_FFFF	RWX	DDR Non-Cached Access - 256 MB
0xD000_0000	0xDFFF_FFFF	RWX	DDR Non-Cached WCB Access - 256 MB CPU Core Complex - NC (AXI Switch Master Port M14)
0xE000_0000	0xFFFF_FFFF	RWX	FIC1 - 512 MB CPU Core Complex - F1 (AXI Switch Master Port M13)
0x01_0000_0000	0x0F_FFFF_FFFF	—	Reserved
0x1C_0000_0000	0x1F_FFFF_FFFF	—	Reserved
0x10_0000_0000	0x13_FFFF_FFFF	RWXC	DDR Cached Access - 16 GB
0x14_0000_0000	0x17_FFFF_FFFF	RWX	DDR Non-Cached Access - 16 GB
0x18_0000_0000	0x1B_FFFF_FFFF	RWX	DDR Non-Cached WCB Access - 16 GB
0x20_0000_0000	0x2F_FFFF_FFFF	RWX	FIC0 - 64 GB
0x30_0000_0000	0x3F_FFFF_FFFF	RWX	FIC1 - 64 GB

Note: Memory Attributes: R - Read, W- Write, X - Execute, C - Cacheable, A - Atomics.

Note: FIC2 is an AXI4 slave interface from the FPGA fabric and does not show up on the MSS memory map. FIC4 is dedicated to the User Crypto Processor and does not show up on the MSS memory map.