Each Global interrupt can be enabled by setting a bit in an Enable
register. There are six Enable registers organized as a contiguous array of 32 bits (6
words). Bit 0 of enable word 0 represents the non-existent interrupt ID 0 and is hardwired
to 0. 64-bit and 32-bit word accesses are supported in the RV64 systems.
Table 1. PLIC Interrupt Enable Register 1 (enable 1)
| PLIC Interrupt Enable Register 1 (enable 1) |
| Base Address =
0x0C00_2000 |
| Bits |
Field Name |
Attributes |
Reset |
Description |
| 0 |
Interrupt 0 Enable |
RW |
X |
Non-existent Global interrupt 0 is hardwired to zero. |
| 1 |
Interrupt 1 Enable |
RW |
X |
Enable bit for Global interrupt 1 |
| 2 |
Interrupt 2 Enable |
RW |
X |
Enable bit for Global interrupt 2 |
| ... |
| 31 |
Interrupt 31 Enable |
RW |
X |
Enable bit for Global interrupt 31 |
Table 2. PLIC Interrupt Enable Register 6 (enable 6)
| PLIC Interrupt Enable Register 6 (enable 6) |
| Base Address =
0x0C00_201C |
| Bits |
Field Name |
Attributes |
Reset |
Description |
| 0 |
Interrupt 160 Enable |
RW |
X |
Enable bit for Global interrupt 160 |
| ... |
| 25 |
Interrupt 186 Enable |
RW |
X |
Enable bit for Global interrupt 186 |
| [31:26] |
Reserved |
WIRI |
X |
— |