The following table lists the generic signals of the MSS DDR Subsystem.
| Signal Name | Direction | Description |
|---|---|---|
| REF_CLK REF_CLK_N | Input | Input PADs for reference clock source. The PADs can be connected to a 100/125 MHz off-chip oscillator. |
| MSS_SYS_RESET_N_F2M | Input | Active-low asynchronous MSS reset. MSS_SYS_RESET_N_F2M must be connected to the DEVICE_INIT_DONE signal of the PFSOC_INIT_MONITOR IP. |
| REFCLK_0_PLL_NW (optional) | Input | Reference clock to the MSS/ DDR PLL. |
| MSS_RESET_N_M2F | Output | Active-low MSS Reset signal for the fabric logic. |
| PLL_CPU_LOCK_M2F | Output | Lock signal to indicate that the MSS PLL is locked on to the reference clock. |
| PLL_DDR_LOCK_M2F | Output | Lock signal to indicate that the DDR PLL is locked on to the reference clock. |