Transmit and Receive FIFOs

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The QSPI controller embeds two FIFOs for receive and transmit, as shown in Figure 1 . These FIFOs are accessible through ReceiveData and TransmitData registers. Writing to the TransmitData register causes the data to be written to the transmit FIFO. This is emptied by the transmit logic. Similarly, reading from the ReceiveData register causes the data to be read from the receive FIFO.