MSS DDR Controller Features

The following table lists the MSS DDR controller features.

Table 1. MSS DDR Controller Features
Feature	Description
Supported Devices	DDR3, DDR3L, DDR4, LPDDR3, and LPDDR4.
ECC	ECC is supported for DDR3 and DDR4.¹
Memory Initialization	Automatic Memory initialization by the E51 monitor core.
PHY	DFI 4.0 compliant PHY.
Interfaces	AXI 128-bit interface for processor cores in the CPU Core Complex. AXI 64-bit interface from the AXI Switch via Fabric Interface Controller (FIC0) for masters in the fabric.
Periodic Functions	Automatic refresh and ZQ calibration functions.
Operational Modes	Single read/write and multi-burst capability. Half-Rate Controller Frequency mode. Additive Latency modes (0, CL-1, CL-2). Two cycle timing (2T) timing on the SDRAM address and control signals.
Supported Configurations	16/32 data I/Os (18/36 data I/Os with ECC). See Supported Configurations.
Supported Device Packages	Single and Dual Rank Components Dual Die Components Single and Dual Rank DIMMs

Note:

1.PolarFire SoC FCSG325 device packages do not support ECC and only support 16-bit DDR bus width.