Supervisor Cause Register (scause)

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When a trap is received in Supervisor mode, scause is written with a code indicating the event that caused the trap. When the event is an interrupt, the most significant bit (MSb) of scause is set to 1, and the least significant bits (LSb) indicate the interrupt number, using the same encoding as the bit positions in sip. For example, a Supervisor Timer interrupt causes scause to be set to 0x8000_0000_0000_0005. scause is also used to indicate the cause of synchronous exceptions, if the MSb of scause is set to 0.

Table 1. Supervisor Cause Register (scause)
Bits Field Name Attributes Description
[62:0] Exception Code WLRL A code identifying the last exception. Supervisor Interrupt Exception codes are listed in Table 2.
63 Interrupt WARL 1 if the trap was caused by an interrupt; 0 otherwise.
Table 2. Supervisor Interrupt Exception Codes
Interrupt Exception Code Description

1

1

1

1

1

1

1

0

1

2-4

5

6-8

9

≥10

Reserved

Supervisor software interrupt

Reserved

Supervisor timer interrupt

Reserved

Supervisor external interrupt

Reserved

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

2

3

4

5

6

7

8

9-11

12

13

14

15

≥16

Instruction address misaligned

Instruction access fault

Illegal instruction

Breakpoint

Reserved

Load access fault

Store/AMO address misaligned

Store/AMO access fault

Environment call from U-mode

Reserved

Instruction page fault

Load page fault

Reserved

Store/AMO page fault

Reserved