The L2 cache controller register map is described in the following table.
Offset | Width | Attributes | Register Name | Notes |
---|---|---|---|---|
0x000 0x008 |
4B 1B |
RO RW |
Config WayEnable |
Information on the configuration of the L2 cache Way enable register |
0x040 0x100 0x108 0x120 0x128 0x140 0x148 0x160 0x168 |
4B 8B 4B 8B 8B 8B 4B 8B 4B |
RW RO RO RO RO RO RO RO RO |
ECCInjectError ECCDirFixAddr ECCDirFixCount ECCDirFailAddr ECCDirFailCount ECCDataFixAddr ECCDataFixCount ECCDataFailAddr ECCDataFailCount |
ECC error injection register Address of most recently corrected metadata error Count of corrected metadata errors Address of most recent uncorrectable metadata error Count of uncorrectable metadata errors Address of most recently corrected data error Count of corrected data errors Address of most recent uncorrectable data error Count of uncorrectable data errors |
0x200 0x240 |
8B 4B |
WO WO |
Flush64 Flush32 |
Flush cache block, 64-bit address Flush cache block, 32-bit address |
0x800 0x808 0x810 0x818 0x820 0x828 0x830 0x838 0x840 0x848 0x850 0x858 0x860 0x868 0x870 |
8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B |
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW |
Master 0 way mask register Master 1 way mask register Master 2 way mask register Master 3 way mask register Master 4 way mask register Master 5 way mask register Master 6 way mask register Master 7 way mask register Master 8 way mask register Master 9 way mask register Master 10 way mask register Master 11 way mask register Master 12 way mask register Master 13 way mask register Master 14 way mask register |
DMA AXI4_front_port ID#0 AXI4_front_port ID#1 AXI4_front_port ID#2 AXI4_front_port ID#3 Hart 0 dCache MMIO Hart 0 iCache Hart 1 dCache Hart 1 iCache Hart 2 dCache Hart 2 iCache Hart 3 dCache Hart 3 iCache Hart 4 dCache Hart 4 ICache |