AXI4 masters implemented in the fabric access the DDR memory through FIC0 (Fabric Interface Controller), the AXI Switch, and the MSS DDR Subsystem, as shown in the following figure.
Figure 1. Functional Example - 2
For the overall PolarFire SoC MSS memory map which covers the memory map of FIC0, CPU Core Complex, AXI Switch, and Seg1 segmentation block, and the MSS DDR Controller (cached and uncached), see MSS Memory Map.