Machine Interrupt Delegation Register (mideleg)

The register description of the mideleg register is provided in the following table.

Table 1. Machine Interrupt Delegation Register (`mideleg`)
Bits	Attributes	Description
0	WARL	Reserved
1	WARL	Supervisor software interrupt
[4:2]	WARL	Reserved
5	WARL	Supervisor timer interrupt
[8:6]	WARL	Reserved
9	WARL	Supervisor external interrupt
[63:10]	WARL	Reserved