The CPU Core Complex supports two hardware breakpoint registers, which can be flexibly shared between Debug mode and Machine mode.
When a breakpoint register is selected with tselect, the other CSRs access the following information for the selected breakpoint:
| TDR CSRs when used as Breakpoints | ||
|---|---|---|
| CSR Name | Breakpoint Alias | Description |
|
tselect tdata1 tdata2 tdata3 |
tselect mcontrol maddress N/A |
Breakpoint selection index Breakpoint Match control Breakpoint Match address Reserved |