The MSS includes the following fabric interfaces for interfacing FPGA fabric with the CPU Core Complex:
Three 64-bit AXI4 FICs:
FIC0: For data transfers to/from the fabric. FIC0 is connected as both master and slave (on the AXI Switch).
FIC1: For data transfers to/from the fabric and PCIe Controller
Hard block in the FPGA. FIC1 is also connected as both master and slave.
FIC2: For interfacing with the DDR Controller inside the MSS block. FIC2 provides a slave interface to the MSS, FIC2 must be connected to a master in the fabric.
One APB 32-bit FIC3 to provide APB interface to the FPGA fabric. FIC3 provides a master interface to the MSS, FIC3 must be connected to a slave in the fabric.
The AHB 32-bit User Crypto Processor interface is called FIC4.