Core Local Interrupt Controller

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The CLINT includes memory-mapped CSRs for enabling software and timer interrupts. The CLINT register map is provided in the following table.

Table 1. CLINT Register Map
Address Width Attributes Description Notes

0x0200_0000

0x0200_0004

0x0200_0008

0x0200_000C

0x0200_0010

4B

4B

4B

4B

4B

RW

RW

RW

RW

RW

msip for Hart0

msip for Hart1

msip for Hart2

msip for Hart3

msip for Hart4

MSIP Registers
0x0200_0014

...

0x0200_3FFF

Reserved

0x0200_4000

0x0200_4008

0x0200_4010

0x0200_4018

0x0200_4020

8B

8B

8B

8B

8B

RW

RW

RW

RW

RW

mtimecmp for Hart0

mtimecmp for Hart1

mtimecmp for Hart2

mtimecmp for Hart3

mtimecmp for Hart 4

Timer compare register
0x0200_4028

...

0x0200_BFF7

Reserved
0x0200_BFF8 8B RW mtime Timer register
0x0200_C000

...

0x0200_FFFF

Reserved

The following sections describe the CLINT CSRs.