The SPI controller embeds two 4 × 32 (depth × width) FIFOs for receive and transmit, as shown in Figure 1. These FIFOs are accessible through RX data and TX data registers. Writing to the TX data register causes the data to be written to the transmit FIFO. This is emptied by the transmit logic. Similarly, reading from the RX data register causes the data to be read from the receive FIFO.