GEM includes the SGMII functional block, which provides the SGMII interface between GEM and Ethernet PHY. The SGMII block provides the following functionalities:
Clock Domain Recovery (CDR) of received 125 MHz clock
Serializing or De-serializing
PLL for synthesis of a 125 MHz transmit clock
The
SGMII block routes the data to the PHY through the dedicated I/O BANK 5.