To signal the completion of executing an interrupt handler, the processor core writes the received interrupt ID to the Claim/Complete register. The PLIC does not check whether the completion ID is the same as the last claim ID for that target. If the completion ID does not match an interrupt source that is currently enabled for the target, the completion is ignored.
| Base Address = 0x0C20_0004 | ||||
|---|---|---|---|---|
| Bits | Field Name | Attributes | Reset | Description |
| [31:0] | Interrupt Claim | RW | X | A read of zero indicates that no interrupts are pending. A non-zero read contains the ID of the highest pending interrupt. A write to this register signals completion of the interrupt ID written. |