Memory Protection Unit

Random access to memory regions by any non-CPU master can corrupt the memory and the overall system. To avoid random access to memory, the PolarFire SoC MSS includes a built-in Memory Protection Unit (MPU) for each master. The GEM0, GEM1, eMMC, USB, SCB, Crypto Processor, Trace, FIC0, FIC1, and FIC2 master blocks interface with an MPU. The MPU can be used to create access regions in memories for a particular master and define privileges to those access regions. The access regions are created by setting the Physical Memory Protection (PMP) registers inside an MPU. The privileges are also defined by setting particular bits of the PMP registers.

At Reset, access to the MSS is not provided until the access regions of the required MPUs are created. Only the SCB can bypass the MPU protection and access the MSS in System mode. MPUs monitor transactions on the AXI read and write channels and only legal accesses pass through. Illegal transactions are not allowed to pass from MPU to the AXI switch, and the MPU initiates AXI response transaction.

MPUs are connected to the APB bus and accessible from the offset 0x20005000. The address bits [11:8] select the MPU block and bits [7:0] the register within the MPU. The following table lists the MPU, the master block it belongs to, address offset of the MPU, and the number of PMP registers inside that MPU. The number of PMP registers represent the number of access regions that can be created for that master. For example, MPU1 belongs to FIC0 and 16 access regions can be created and privileged using the 16 PMP registers.