The WayEnable register determines which ways of the L2 cache controller are enabled as cache. Cache ways which are not enabled, are mapped into the L2-LIM as described in MSS Memory Map.
This register is initialized to 0 on reset and may only be increased. This means that, out of Reset, only a single L2 cache way is enabled as one cache way must always remain enabled. Once a cache way is enabled, the only way to map it back into the L2-LIM address space is by a Reset.
Register Offset | 0x008 | |||
---|---|---|---|---|
Bits | Field Name | Attributes | Reset | Description |
[7:0] | Way Enable | RW | 0 | Way indexes less than or equal to this register value may be used by the cache |
[63:8] | Reserved | RW | — | — |