The idle register specifies the number of idle cycles before a buffer is automatically emptied. WCB can be configured to be idle for up to 255 cycles.
When idle is set to 0, WCB is disabled and writes to the WCB address range bypass WCB.
| Idle Configuration Register (idle) | ||||
|---|---|---|---|---|
| Register Offset | 0 | |||
| Bits | Field Name | Attributes | Reset | Description |
| [7:0] | idle | RW | 16 | Number of idle cycles before flushing a buffer. Setting to 0 disables WCB and all buffers are emptied. |
| [31:8] | Reserved | RW | X | — |