The following acronyms are used in this document.
| Acronym | Expanded |
|---|---|
| ACR | Acceptance Code Register |
| AHB | Advanced High-performance Bus |
| AMP | Asymmetric Multi-Processing |
| AMR | Acceptance Mask Register |
| APB | Advanced Peripheral Bus |
| BEU | Bus Error Unit |
| CAN | Control Area Network |
| CDC | Clock Domain Crossing |
| CLINT | Core Local Interrupt Controller. |
| CSR | Control and STATUS Register |
| dCache | Data Cache |
| DMA | Direct Memory Access |
| DTIM | Data Tightly Integrated Memory (also called as SRAM) |
| ECC | Error Correction Code |
| EDAC | Error Detection and Correction |
| EIP | Electrical Interconnect and Package |
| eMMC | embedded Multi-Media Controller |
| eNVM | embedded Non-Volatile Memory/BootFlash |
| FIC | Fabric Interface Controller |
| FSBL | First Stage Boot Loader |
| GEM | Gigabit Ethernet MAC |
| GPIO | General Purpose Inputs/Outputs |
| Hart | Hardware thread/core/processor core |
| HLP | Higher-layer Protocols |
| I2C | Inter-Integrated Circuit |
| iCache | Instruction Cache |
| IrDA | Infrared Data Association |
| IRQ | Interrupt Request |
| ISA | Instruction Set Architecture |
| ITIM | Instruction Tightly Integrated Memory |
| JTAG | Joint Test Action Group |
| LIM | Loosely Integrated Memory |
| LIN | Local Interconnect Network |
| LSB | Least Significant Bit |
| MAC | Media Access Controller |
| MMU | Memory Management Unit |
| MMUART | Multi-mode Universal Asynchronous/Synchronous Receiver/Transmitter |
| MPU | Memory Protection Unit |
| MSB | Most Significant Bit |
| MSS | Microprocessor Sub-System |
| OTG | On-The-Go |
| POR | Power-on Reset |
| PLIC | Platform-Level Interrupt Controller |
| PMP | Physical Memory Protection |
| PTE | Page Table Entry |
| QSPI | Quad Serial Peripheral Interface |
| RO | Read only |
| ROM | Read-only Memory |
| RTC | Real-time Counter |
| RV64IMAC |
RISC-V 64-bit ISA, where, I = Base Integer Instruction Set M = Standard Extension for Integer Multiplication and Division A = Standard Extension for Atomic Instructions C = Standard Extension for Compressed Instructions |
| RV64GC |
RISC-V 64-bit ISA, where, G=IMAFD I = Base Integer Instruction Set M = Standard Extension for Integer Multiplication and Division A = Standard Extension for Atomic Instructions F = Standard Extension for Single-Precision Floating-Point D = Standard Extension for Double-Precision Floating-Point C = Standard Extension for Compressed Instructions |
| RW | Read/Write |
| RZI | Return to Zero Inverted |
| SCB | System Controller Bus |
| SCL | Serial Clock Line |
SD |
Secure Digital |
SDIO |
Secure Digital Input Output |
| SDS | Smart Distributed System |
| SECDED | Single-Error Correction and Double-Error Detection |
| SMBus | System Management Bus |
SPI |
Serial Peripheral Interface |
| SST | Single-shot Transmission |
| TLB | Translation Look-aside Buffer |
| USB | Universal Serial Bus |
| VIPT | Virtually Indexed Physically Tagged |
| WIRI | Writes-Ignored, Reads-Ignore field. A read-only register field reserved for future use. Writes to the field are ignored, and reads should ignore the value returned. |
| WARL | Write-Any Read-Legal field. A register field that can be written with any value, but returns only supported values when read. |
| WIRI | Writes-Ignored, Reads-Ignore field. A read-only register field reserved for future use. Writes to the field are ignored, and reads should ignore the value returned. |
| WLRL | Write-Legal, Read-Legal field. A register field that should only be written with legal values and that only returns legal value if last written with a legal value. |
| WO | Write only |
| WPRI | Writes-Preserve Reads-Ignore field. A register field that may contain unknown information. Reads should ignore the value returned, but writes to the whole register should preserve the original value. |
| XIP | Execute In Place |