The iCache memory consists of a dedicated 32 KB 8-way set-associative,
Virtually Indexed Physically Tagged (VIPT) instruction cache memory with a line size of 64
bytes. The access latency of any block in the iCache is one clock cycle. iCache is not
coherent with the platform memory system. Writes to iCache must be synchronized with the
instruction fetch stream by executing the FENCE.I instruction.
A cache line fill triggers a burst access outside the CPU Core Complex. The U54 processor core caches instructions from executable addresses, with the exception of ITIM. See CPU Memory Map for all executable address regions, which are denoted by the attribute X. Trying to execute an instruction from a non-executable address results in a trap.