Bank Management

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The controller includes bank management module(s) to monitor the status of each DDR SDRAM bank. Banks are opened/closed only when necessary, minimizing access delays. Up to 64 banks can be managed at one time. Read/write requests are issued with minimal idle time between commands, typically limited only by the DDR timing specifications. This results in minimal between requests, enabling up to 100% memory throughput for sequential accesses (not including refresh and ZQ-calibration commands).