The PLIC memory map is designed for naturally aligned 32-bit memory accesses.
| PLIC Memory Map | ||||
|---|---|---|---|---|
| Address | Width | Attributes | Description | Notes |
|
0x0C00_0000 0x0C00_0004 0x0C00_0008 ... 0x0C00_02D0 |
4B 4B 4B |
RW RW RW |
Reserved source 1 priority source 2 priority ... source 186 priority |
See Table 1. |
| 0xC00_02D4 ... 0x0C00_0FFF |
— | — | Reserved | — |
| 0xC00_1000 ... 0x0C00_1014 |
4B ... 4B |
RO ... RO |
Start of pending array ... Last word of pending array |
See Table 1. |
| 0x0C00_1018 ... 0x0C00_1FFF |
— | — | Reserved | — |
| 0x0C00_2000 ... 0x0C00_2014 |
4B ... 4B |
RW ... RW |
Start of Hart 0 M-mode enables ... End of Hart 0 M-mode enables |
See Table 1. |
| 0x0C00_2018 ... 0x0C00_207F |
— | — | Reserved | — |
| 0x0C00_2080 ... 0x0C00_2094 |
4B ... 4B |
RW ... RW |
Hart 1 M-mode enables ... End of Hart 1 M-mode enables |
Same layout as Hart 0 M-mode enables |
| 0x0C00_2100 ... 0x0C00_2114 |
4B ... 4B |
RW ... RW |
Hart 1 S-mode enables ... End of Hart 1 S-mode enables |
|
| 0x0C00_2180 ... 0x0C00_2194 |
4B ... 4B |
RW ... RW |
Hart 2 M-mode enables ... End of Hart 2 M-mode enables |
|
| 0x0C00_2200 ... 0x0C00_2214 |
4B ... 4B |
RW ... RW |
Hart 2 S-mode enables ... End of Hart 2 S-mode enables |
|
| 0x0C00_2280 ... 0x0C00_2294 |
4B ... 4B |
RW ... RW |
Hart 3 M-mode enables ... End of Hart 3 M-mode enables |
|
| 0x0C00_2300 ... 0x0C00_2314 |
4B ... 4B |
RW ... RW |
Hart 3 S-mode enables ... End of Hart 3 S-mode enables |
|
| 0x0C00_2380 ... 0x0C00_2394 |
4B ... 4B |
RW ... RW |
Hart 4 M-mode enables ... End of Hart 4 M-mode enables |
|
| 0x0C00_2400 ... 0x0C00_2414 |
4B ... 4B |
RW ... RW |
Hart 4 S-mode enables ... End of Hart 4 S-mode enables |
|
| 0x0C00_2480 ... 0x0C1F_FFFF |
— | — | Reserved | |
| 0x0C20_0000 0x0C20_0004 |
4B 4B |
RW RW |
Hart 0 M-mode priority threshold Hart 0 M-mode claim/complete |
See Table 1 and Table 1. |
| 0x0C20_1000 0x0C20_1004 |
4B 4B |
RW RW |
Hart 1 M-mode priority threshold Hart 1 M-mode claim/complete |
|
| 0x0C20_2000 0x0C20_2004 |
4B 4B |
RW RW |
Hart 1 S-mode priority threshold Hart 1 S-mode claim/complete |
|
| 0x0C20_3000 0x0C20_3004 |
4B 4B |
RW RW |
Hart 2 M-mode priority threshold Hart 2 M-mode claim/complete |
|
| 0x0C20_4000 0x0C20_4004 |
4B 4B |
RW RW |
Hart 2 S-mode priority threshold Hart 2 S-mode claim/complete |
|
| 0x0C20_5000 0x0C20_5004 |
4B 4B |
RW RW |
Hart 3 M-mode priority threshold Hart 3 M-mode claim/complete |
|
| 0x0C20_6000 0x0C20_6004 |
4B 4B |
RW RW |
Hart 3 S-mode priority threshold Hart 3 S-mode claim/complete |
— |
| 0x0C20_7000 0x0C20_7004 |
4B 4B |
RW RW |
Hart 4 M-mode priority threshold Hart 4 M-mode claim/complete |
|
| 0x0C20_8000 0x0C20_8004 |
4B 4B |
RW RW |
Hart 4 S-mode priority threshold Hart 4 S-mode claim/complete |
|