Supported Configurations

The following table lists the supported memory configurations per DDR I/O lane for 16-bit and 32-bit data widths with and without ECC. Data lanes 0 to 3 each contain eight data bits and lane 4 contains 2 or 4 ECC bits when ECC is enabled.

Table 1. DDR Memory Lane Support
Memory Configuration	No. of Data/ECC I/Os	Lane 0 (Data)	Lane 1 (Data)	Lane 2 (Data)	Lane 3 (Data)	Lane 4 (ECC)
5x DDRx8 with ECC	36	DDRx8	DDRx8	DDRx8	DDRx8	DDRx8 (4 used)
4x DDRx8 no ECC	32	DDRx8	DDRx8	DDRx8	DDRx8	Not used
3x DDRx16 with ECC	36	DDRx16		DDRx16		DDRx16 (4 used)
2x DDRx16 no ECC	32	DDRx16		DDRx16		not used
3x DDRx16 with ECC	18	DDRx8	DDRx8	not used	not used	DDRx8 (2 used)
2x DDRx16 no ECC	16	DDRx8	DDRx8			not used
1x DDRx16 with ECC	18	DDRx16				DDRx16 (2 used)
1x DDRx16 no ECC	16	DDRx16				not used
1x DDRx32 no ECC	32	DDRx32				not used
Important: ECC is supported only for DDR3 and DDR4. Lane 4 is only 4-bits wide, the upper data bits on the DDR memory are not connected. In PolarFire SoC MSS Configurator, when the DQ width is set to 16 with ECC enabled, four extra pins DQ[16], DQ[17], DQ[18], and DQ[19] are available. In this case, DQ[16] and DQ[17] are used for ECC, while DQ[18] and DQ[19] are used for write calibration in training.

Each data lane can be connected to a single DDR memory component or DIMM. A dual-die device is supported for a component. The maximum supported number of memory address lines is 18 plus two chip-enable signals (dual-rank) giving a maximum memory capacity (ignoring ECC) of 8 GB.