Revision History

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The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Revision Date Description
F 11/2022
E 06/2022
  • Added Branch Prediction.
  • Added the following information in AXI Switch:
    • Added Table 2 that describes Master and Slave connectivity.
    • Added Table 3 that lists the address ranges of each slave port on the AXI switch.
  • Added a note regarding the rules which apply during the selection I/Os of MSS peripherals, see MSS I/Os.
  • Added a note that describes the DDR I/O setting when DQ width is set to 16 with ECC enabled, see Supported Configurations.
  • Added a note regarding SHIELD signals under Table 1.
D 05/2022
  • Enabled ‘Ask A Question’ hyperlink for each section in the document.
  • Updated the description of the FABRIC_RESET signal, see Table 1.
  • Added a note on routing MSS I2C I/O to Fabric, see Functional Description.
C 12/2021
  • Updated the fabric to MSS interrupt name from “fabric_f2h” to “MSS_INT_F2M” in Table 1.
  • Added the minimum AHB or APB clock frequency requirement for driving eNVM. See AXI-to-AHB.
  • Updated DDR3 and LPDDR3 speed in Table 1.
  • Removed MSS-specific power management information from Clocking.
  • Added information about SOFT_RESET_CR system register, which is used to Reset all MSS peripherals in Resets and Peripherals.
  • Updated the Boot Process section to include information about MSS boot modes.
  • Updated the Bus Error Unit (BEU) section to mention that BEUs are used for reporting errors only in L1 instruction and data caches.
  • Updated the information about how to reset FICs, see FIC Reset.
B 08/2021
A 04/2021
  • Converted the document type to MSS Technical Reference Manual from MSS User Guide.
  • Document converted to Microchip format and document number changed from UG0880 to DS60001702A
3.0 09/2020
2.0 04/2020
1.0 10/2019 This the first publication of this document.