The DDR PHY is included in the MSS DDR I/O Bank 6, which consists of I/O lanes and the training logic. The integrated PHY provides a physical interface to DDR3, DDR4, LPDDR3, and LPDDR4 SDRAM devices. It receives commands from the DDR controller and generates the DDR memory signals required to access the external DDR memory. The training logic manages DFI 4.0 training requests between the I/O lane and the DDR controller.