Trace

The MSS includes a Trace block to enable an external system to run trace functionalities via the JTAG interface. The Trace block supports the following features:

• Instruction trace of all five processor cores.
• Full AXI trace of a selectable slave interface on the main AXI switch.
• Trace of AXI transactions (address only) on L2 cache in the CPU Core Complex.
• Trace of 40-fabric signals via the Electrical Interconnect and Package (EIP) interface (40 data plus clock and valid signal).
• Interfaced via an external JTAG interface.
• An AXI communicator module is implemented allowing the firmware running on the CPU Core Complex to configure the trace system
• A Virtual Console is implemented allowing message passing between the processor cores and an external trace system.

For more information on the features, components, and use models of Trace, see SoftConsole User Guide (to be published).