Initialization Sequence

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The following steps summarize the initialization sequence of the MSS DDR Controller:

The asynchronous SYS_RESET_N and PLL_LOCK signals are de-asserted.

The E51 monitor core initializes the MSS DDR Subsystem.

The MSS_RESET_N_M2F signal is asserted to indicate that initialization is completed. This signal can be monitored from the fabric.