The DMA engine contains an independent set of registers for each channel. Each channel’s registers start at the offset 0x1000 so that the base address for any DMA channel is: DMA Base Address + (0x1000 × Channel ID). The register map of a DMA channel is described in the following table.
DMA Memory Map per channel | ||||
---|---|---|---|---|
Channel Base Address | DMA Base Address + (0x1000 × Channel ID) | |||
Offset | Width | Attributes | Register Name | Description |
0x000 | 4B | RW | Control | Channel control register |
0x004 | 4B | RW | NextConfig | Next transfer type |
0x008 | 8B | RW | NextBytes | Number of bytes to move |
0x010 | 8B | RW | NextDestination | Destination start address |
0x018 | 8B | RW | NextSource | Source start address |
0x104 | 4B | R | ExecConfig | Active transfer type |
0x108 | 8B | R | ExecBytes | Number of bytes remaining |
0x110 | 8B | R | ExecDestination | Destination current address |
0x118 | 8B | R | ExecSource | Source current address |
The following sections describe the Control and Status registers of a channel.