The U54 core supports the RISC-V standard Atomic (A) extension on regions of the Memory Map denoted by the attribute A in CPU Memory Map. Atomic memory operations to regions that do not support them generate an access exception precisely at the core.
The load-reserved and store-conditional instructions are only supported on cached regions, hence generate an access exception on DTIM and other uncached memory regions.
See The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.1 for more information on the instructions added by this extension.