Time Stamping Unit

TSU implements a timer, which counts the time in seconds and nanoseconds format. This block is supplied with tsu_clk, which ranges from 5 MHz to 400 MHz. The timer is implemented as a 94-bit register as follows.

• The upper 48 bits counts seconds
• The next 30 bits counts nanoseconds
• The lower 16 bits counts sub nanoseconds
  Note: sub nanoseconds is a time-interval measurement unit which is shorter than nanoseconds.

  The timer increments at each tsu_clk period and an interrupt is generated in the seconds increment. The timer value can be read, written, and adjusted through the APB interface.

There are two modes of operation:

• Timer Adjust Mode
• Increment Mode