ECC is supported only for DDR3 and DDR4. When ECC is enabled, the DDR controller computes a 4-bit ECC for every 32-bit data to support SECDED. A write operation computes and stores an ECC along with the data, and a read operation reads and checks the data against the stored ECC. Therefore, when ECC is enabled, single or double-bit errors may be received when reading uninitialized memory locations. To prevent this, all memory locations must be written to before being read. ECC can be enabled using the Standalone MSS Configurator -> DDR Memory -> DDR Topology tab.