Asymmetric Multi-Processing (AMP) APB Bus

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All APB peripherals are connected to S5 slave port of the AXI Switch using the AXI-to-AHB and
 AHB-to-APB bridges as shown in Figure 1. Multiple processor cores and fabric interfaces arbitrate for access to the APB slaves resulting in a variable access latency based on system activity. This may cause system issues when the CPU Core Complex operates in the AMP mode with two separate operating systems running on different processor cores.

The AMP APB bus system is used to connect to the S6 slave port of the AXI Switch using system addresses 0x2800_0000-0x2FFF_FFFF (Figure 1). Each APB peripheral can be configured at device start-up to be connected to the main APB bus (0x2000_0000-0x203F_FFFF) or to the secondary AMP APB bus (0x2800_0000-0x2FFF_FFFF). For more information about the default base addresses and alternate base addresses of peripherals, see MSS Memory Map. This allows two independent access systems from the CPU Core Complex to peripherals. Devices specified as DUAL in Table 1 may be mapped to the AMP APB bus structure.

In normal system operation, per-processor PMP blocks must be programmed to allow only the appropriate processor regions to which the APB peripherals are mapped. If the PMP blocks are incorrectly configured and a device is accessed in the wrong region then the hardware will generate a PSLVERR response which is reported to the processor core as an AXI response error.