Interrupt latency is four cycles and depends on the numbers of cycles it
takes from the signaling of the interrupt to the first instruction fetch of the handler.
Global interrupts routed through the PLIC incur an additional latency of three cycles,
where the PLIC is clocked by the user_clock. If interrupt handler is cached or located in
ITIM, the total latency (cycles) of a Global interrupt is 4 + 3 × [(core clock
(Hz)/user_clock (Hz)].
Additional latency from a peripheral source is not included. Moreover, the Hart does not ignore an arithmetic instruction like “Divide” that is in the execution pipeline. Hence, if an interrupt handler tries to use a register which is the destination register of a divide instruction, the pipeline stalls until the completion of the divide instruction.