Processor cores access DDR memory using the MSS DDR Subsystem via Seg0 (Segmentation block) as shown in the following figure.
Figure 1. Functional Example - 1
For the overall PolarFire SoC MSS memory map which covers the memory map of the CPU Core Complex, L2 Cache, Seg0 Segmentation block, and the MSS DDR Controller, see MSS Memory Map.