STATUS Register

When an illegal transaction occurs, MPU performs the following events:

The AXI transaction to the main AXI switch is suppressed and stored internally. An interrupt is generated to inform the processor that a violation occurred. The processor can ignore this interrupt.
After the completion of all outstanding AXI transactions queued in the AXI switch, the MPU terminates the illegal transaction by initiating decode error response (DECERR=2’b11) on the read/write response bus. This response is required to maintain the AXI ordering rules. The read and write channels are independent of each other.
The 64-bit long status register captures a denied address. Once a failure is captured, subsequent denied accesses are not captured until the register is cleared by the MPU status clear system register. On the APB bus, this 64-bit register is read as two 32-bit values. The bit field definitions of the STATUS Register are given in the following table.

Table 1. STATUS Register
Bits	Field	Description
37:0	Address	38-bit failed address
38	Write	0=Read 1=Write
42:39	ID	AXI ID of failure (4-bits)
43	Failed	Indicates Failure occurred, cleared via a system register bit

The MPU9 block, between the SCB and the AXI Switch, is configured so that AXI transaction with ID=1 bypass the MPU protection. The SCB only initiates AXI=1 ID messages when the SCB bus request is a system request (non-user) indicating that the AXI command was initiated by the secure System Controller firmware and must be given access.