The DDR PLL, external to the MSS, generates the required clocks for the MSS DDR Controller and the DDR PHY. These clocks are distributed throughout the subsystem using HS_IO_CLK routes, dedicated pads, and fabric clock routing. The DDR PLL sources the reference frequency from an off-chip 100/125 MHz oscillator.
The PLL generates the following clocks:
The HS_IO_CLK and REF_CLK clocks are generated with the same frequency and phase. The REF_CLK to SYS_CLK ratio is 4:1.