Contents

Introduction References 3. Acronyms 4. Features 5. Detailed Block Diagram 6. Functional Blocks 6.1. CPU Core Complex 6.1.1. E51 RISC-V Monitor Core 6.1.1.1. Instruction Fetch Unit 6.1.1.2. Execution Pipeline 6.1.1.3. ITIM 6.1.1.4. DTIM 6.1.1.5. Hardware Performance Monitor 6.1.1.6. ECC 6.1.1.6.1. ECC Reporting 6.1.2. U54 RISC-V Application Cores 6.1.2.1. Instruction Fetch Unit 6.1.2.2. Execution Pipeline 6.1.2.3. Instruction Cache 6.1.2.4. ITIM 6.1.2.5. Data Cache 6.1.2.6. Atomic Memory Operations 6.1.2.7. Floating Point Unit 6.1.2.8. MMU 6.1.2.9. ECC 6.1.2.10. Hardware Performance Monitor 6.1.3. CPU Memory Map 6.1.4. Physical Memory Protection 6.1.4.1. PMP Configuration Register (pmpcfg) 6.1.4.1.1. Locking and Privilege Mode 6.1.4.2. PMP Address Register (pmpaddr) 6.1.5. L2 Cache 6.1.6. L2 Cache Controller 6.1.6.1. Functional Description 6.1.6.1.1. Way Enable and the L2 LIM 6.1.6.1.2. Way Masking and Locking 6.1.6.1.3. L2 Cache Power Control 6.1.6.1.4. Scratchpad 6.1.6.1.5. L2 ECC 6.1.6.2. Register Map 6.1.6.3. Register Descriptions 6.1.6.3.1. Cache Configuration Register (Config) 6.1.6.3.2. Way Enable Register (WayEnable) 6.1.6.3.3. ECC Error Injection Register (ECCInjectError) 6.1.6.3.4. ECC Directory Fix Address (ECCDirFixAddr) 6.1.6.3.5. ECC Directory Fix Count (ECCDirFixCount) 6.1.6.3.6. ECC Directory Fail Address (ECCDirFailAddr) 6.1.6.3.7. ECC Directory Fail Count (ECCDirFailCount) 6.1.6.3.8. ECC Data Fix Address (ECCDataFixAddr) 6.1.6.3.9. ECC Data Fix Count (ECCDataFixCount) 6.1.6.3.10. ECC Data Fail Address (ECCDataFailAddr) 6.1.6.3.11. ECC Data Fail Count (ECCDataFailCount) 6.1.6.3.12. Cache Flush Registers 6.1.6.3.13. Way Mask Registers (WayMaskX) 6.1.7. Branch Prediction 6.1.8. TileLink 6.1.9. External Bus Interfaces 6.1.10. DMA Engine 6.1.10.1. DMA Memory Map 6.1.10.2. Control Register 6.1.10.3. Channel Next Configuration Register (NextConfig) 6.1.10.4. Channel Next Bytes Register (NextBytes) 6.1.10.5. Channel Next Destination Register (NextDestination) 6.1.10.6. Channel Next Source Address (NextSource) 6.1.10.7. Channel Exec Registers 6.1.11. Write Combining Buffer (WCB) 6.1.11.1. Idle Configuration Register (idle) 6.1.12. Bus Error Unit (BEU) 6.1.12.1. BEU Register Map 6.1.12.2. Functional Description 6.1.13. Debug 6.1.13.1. Debug CSRs 6.1.13.1.1. Trace and Debug Register Select (tselect) 6.1.13.1.2. Trace and Debug Data Registers (tdata1–3) 6.1.13.1.3. Debug Control and STATUS Register (dcsr) 6.1.13.1.4. Debug PC (dpc) 6.1.13.1.5. Debug Scratch (dscratch) 6.1.13.2. Breakpoints 6.1.13.2.1. Breakpoint Match Control Register (mcontrol) 6.1.13.2.2. Breakpoint Match Address Register (maddress) 6.1.13.2.3. Breakpoint Execution 6.1.13.2.4. Sharing Breakpoints between Debug and Machine mode 6.1.13.3. Debug Memory Map 6.1.13.3.1. Debug RAM and Program Buffer (0x300–0x3FF) 6.1.13.3.2. Debug ROM (0x800–0xFFF) 6.1.13.3.3. Debug Flags (0x100 – 0x110, 0x400 – 0x7FF) 6.1.13.3.4. Safe Zero Address 6.1.13.4. PolarFire SoC Debug 6.1.13.4.1. Debug Architecture 6.1.13.4.2. Multi-Core Application Debug 6.1.14. Trace 6.1.14.1. Instruction Trace Interface 6.1.14.2. Trace Features 6.1.14.3. Trace Architecture 6.1.14.4. Trace Components 6.1.14.4.1. JTAG Communicator 6.1.14.4.2. JPAM 6.1.14.4.3. Message Infrastructure Bus 6.1.14.4.4. AXI Monitor 0 6.1.14.4.5. AXI Monitor 1 6.1.14.4.6. Virtual Console 6.1.14.4.7. AXI Communicator 6.1.14.4.8. System Memory Buffer (SMB) 6.1.14.4.9. RISC-V Trace 6.1.14.4.10. Fabric Trace 6.1.14.5. Functional Examples 6.1.14.5.1. Processor Trace 6.1.14.5.2. Data Trace on AXI Switch Slave Port 6.1.14.5.3. Address and Data Trace on DDR Controller 6.1.14.5.4. Fabric Trace 6.2. AXI Switch 6.2.1. AXI Switch Arbitration 6.2.2. Quality of Service 6.2.3. AXI Atomic Operations 6.3. Fabric Interface Controllers (FICs) 6.4. Memory Protection Unit 6.4.1. PMPCFG Register Map 6.4.2. PMPCFG Bit Fields 6.4.3. STATUS Register 6.5. Segmentation Blocks 6.6. AXI-to-AHB 6.7. AHB-to-APB 6.8. Asymmetric Multi-Processing (AMP) APB Bus 6.9. MSS I/Os 6.10. User Crypto Processor 6.11. MSS DDR Memory Controller 6.11.1. Block Diagram 6.11.2. MSS DDR Controller Features 6.11.3. Performance 6.11.4. Supported Configurations 6.11.4.1. Supported DDR4 Memories 6.11.4.2. Supported DDR3 Memories 6.11.4.3. Supported LPDDR4 Memories 6.11.4.4. Supported LPDDR3 Memories 6.11.5. Functional Description 6.11.5.1. Multi-Burst 6.11.5.2. Queue Control 6.11.5.3. Bank Management 6.11.5.4. Frequency Mode 6.11.5.5. ECC 6.11.5.6. Address Mapping 6.11.5.7. DDR PHY 6.11.5.8. Clocking Structure 6.11.5.9. Initialization Sequence 6.11.6. MSS DDR Subsystem Ports 6.11.6.1. Generic Signals 6.11.6.2. SDRAM Interface Signals 6.11.7. Functional Timing Diagrams 6.11.8. Implementation 6.11.9. Functional Examples 6.11.9.1. Accessing DDR Memory from the MSS 6.11.9.2. Accessing DDR Memory from Fabric 6.12. Peripherals 6.12.1. Memory Map 6.12.2. PolarFire SoC Gigabit Ethernet MAC 6.12.2.1. Features 6.12.2.2. Overview 6.12.2.3. Clocking 6.12.2.4. Functional Description 6.12.2.4.1. MAC Transmitter 6.12.2.4.2. MAC Receiver 6.12.2.4.3. Register Interface 6.12.2.4.4. AXI DMA 6.12.2.4.5. MAC Filter 6.12.2.4.6. Time Stamping Unit 6.12.2.4.6.1. Timer Adjust Mode 6.12.2.4.6.2. Increment Mode 6.12.2.4.7. IEEE 1588 Implementation 6.12.2.4.7.1. PTP Strobes 6.12.2.4.7.2. PTP Strobe Usage (GMII) 6.12.2.4.7.3. PTP Strobe Usage (SGMII) 6.12.2.4.8. Time Sensitive Networking 6.12.2.4.8.1. IEEE 802.1 Qav Support – Credit based Shaping 6.12.2.4.8.2. IEEE 802.1 Qbv – Enhancement for Scheduled Traffic 6.12.2.4.8.3. IEEE 802.1 CB Support 6.12.2.4.8.4. IEEE 802.1 Qci Receive Traffic Policing 6.12.2.4.8.5. IEEE 802.3br Support 6.12.2.4.9. PHY Interface 6.12.2.4.9.1. Physical Coding Sublayer 6.12.2.4.9.2. GMII / MII Interface 6.12.2.4.9.3. SGMII 6.12.2.4.9.4. PHY Management Interface 6.12.2.5. Register Address Map 6.12.3. CAN Controller 6.12.3.1. Features 6.12.3.1.1. EDAC 6.12.3.1.2. Reset 6.12.3.2. Functional Description 6.12.3.2.1. CAN Controller Interface Signals 6.12.3.2.2. Transmit Procedures 6.12.3.2.2.1. Procedure for Sending a Message 6.12.3.2.2.2. Remove a Message from a Transmit Holding Register 6.12.3.2.2.3. Single-Shot Transmission 6.12.3.2.3. Receive Procedures 6.12.3.2.3.1. Received Message Processing 6.12.3.2.3.2. Acceptance Filter 6.12.3.2.3.2.1. RTR Auto-Reply 6.12.3.2.3.3. Receive Buffer Linking 6.12.3.3. Register Map 6.12.4. eNVM Controller 6.12.4.1. Features 6.12.4.2. Functional Description 6.12.4.2.1. Data Retention Time 6.12.4.2.2. eNVM Access Time Speed 6.12.4.2.3. R-Bus Access 6.12.4.2.4. C-Bus Access 6.12.4.3. Register Map 6.12.5. Quad SPI with XIP 6.12.5.1. Features 6.12.5.2. Functional Description 6.12.5.2.1. Transmit and Receive FIFOs 6.12.5.2.2. Configuration and Control Logic 6.12.5.3. XIP Operation 6.12.5.4. Register Map 6.12.6. MMUART 6.12.6.1. Features 6.12.6.2. Functional Description 6.12.6.3. Register Map 6.12.7. SPI Controller 6.12.7.1. Features 6.12.7.2. Functional Description 6.12.7.2.1. Transmit and Receive FIFOs 6.12.7.2.2. Configuration and Control Logic 6.12.7.2.3. SPI Clock Generator 6.12.7.3. Register Map 6.12.8. I2C 6.12.8.1. Features 6.12.8.2. Functional Description 6.12.8.2.1. Input Glitch Filter 6.12.8.2.2. Arbitration and Synchronization Logic 6.12.8.2.3. Address Comparator 6.12.8.2.4. Serial Clock Generator 6.12.8.3. Register Map 6.12.9. GPIO 6.12.9.1. Features 6.12.9.2. Functional Description 6.12.9.3. Register Map 6.12.10. Real-time Counter (RTC) 6.12.10.1. Features 6.12.10.2. Functional Description 6.12.10.2.1. Prescaler 6.12.10.2.2. RTC Counter 6.12.10.2.3. Alarm Wake-up Comparator 6.12.10.3. Register Map 6.12.11. Timer 6.12.11.1. Features 6.12.11.2. Functional Description 6.12.11.3. Register Map 6.12.12. Watchdog 6.12.12.1. Features 6.12.12.2. Functional Description 6.12.12.2.1. APB Interface 6.12.12.2.2. 32-Bit Counter 6.12.12.2.3. Timeout Detection 6.12.12.3. Register Map 6.12.13. Universal Serial Bus OTG Controller 6.12.13.1. Features 6.12.13.2. Functional Description 6.12.13.2.1. AHB Master and Slave Interfaces 6.12.13.2.2. CPU Interface 6.12.13.2.3. Endpoints (EP) Control Logic and RAM Control Logic 6.12.13.2.4. Packet Encoding, Decoding, and CRC Block 6.12.13.2.5. PHY Interfaces 6.12.13.3. Register Map 6.12.14. eMMC SD/SDIO 6.12.14.1. Features 6.12.14.2. Functional Description 6.12.14.2.1. Integrated DMA 6.12.14.2.1.1. SDMA 6.12.14.2.1.2. ADMA2 6.12.14.3. Register Map 6.12.15. FRQ Meter 6.12.15.1. Features 6.12.15.2. Functional Description 6.12.15.2.1. Use Models 6.12.15.3. Register Map 6.12.16. M2F Interrupt Controller 6.12.16.1. Features 6.12.16.2. Functional Description 6.12.16.3. Register Map 7. System Registers 8. Interrupts 8.1. Interrupt CSRs 8.1.1. Machine STATUS Register (mstatus) 8.1.2. Machine Interrupt Enable Register (mie) 8.1.3. Machine Interrupt Pending Register (mip) 8.1.4. Machine Cause Register (mcause) 8.1.5. Machine Trap Vector Register (mtvec) 8.2. Supervisor Mode Interrupts 8.2.1. Machine Interrupt Delegation Register (mideleg) 8.2.2. Machine Exception Delegation Register (medeleg) 8.2.3. Supervisor STATUS Register (sstatus) 8.2.4. Supervisor Interrupt Enable Register (sie) 8.2.5. Supervisor Interrupt Pending (sip) 8.2.6. Supervisor Cause Register (scause) 8.2.7. Supervisor Trap Vector (stvec) 8.3. Interrupt Priorities 8.4. Interrupt Latency 8.5. Platform Level Interrupt Controller 8.5.1. PLIC Memory Map 8.5.2. Interrupt Sources 8.5.3. Interrupt Priorities Register 8.5.4. Interrupt Pending Bits 8.5.5. Interrupt Enables 8.5.6. Priority Thresholds 8.5.7. Interrupt Claim Process 8.5.8. Interrupt Completion 8.6. Core Local Interrupt Controller 8.6.1. MSIP Register (msip) 8.6.2. Timer Registers (mtime) 8.6.3. Supervisor Mode Delegation 9. Fabric Interface Controller 9.1. Overview 9.1.1. Address Range 9.2. FIC Reset 9.3. Timing Diagrams 9.4. Configuring FICs 10. Boot Process 11. Resets 12. Clocking 13. MSS Memory Map 14. Revision History 15. Microchip FPGA Support 16. Microchip Information The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service