1.Reading flash immediately after chip
erase using external programming interface may show incorrect data on low supply
voltages (VCC<3V)
Description:
If Chip Erase is performed at low supply voltage
(VCC<3V), a flash read performed immediately after the chip erase
(within 500ms) may show wrong results.
Fix/Workaround:
If chip erase is executed at a low voltage, wait for 500ms
before reading the flash contents.
2.Writing lock bits using SPM command
causes next SPM instruction not to be performed
Description:
After writing memory lock bits, first subsequent flash or
EEPROM erase or write could fail. Writing the lock bits or boot lock
bits from SW will cause the direct subsequent flash or EEPROM write not
to be performed.
Fix/Workaround:
After any memory lock bits are written, perform a
dummy-write to any flash or EEPROM location. Data should contain all 1’s
to avoid changing the content. Wait until RWWSB bit in SPMCSR and EEPE
bit in EECR register becomes zero. Powering off the device after memory
lock bits are written will also resolve the problem.
3.Clock Failure Detection (CFD) doesn't
resume back to original clock with external reset
Description:
If clock failure has occurred when CFD is enabled and
device is operating with 1 MHz fallback clock then external reset
doesn't cause the system to try to resume back to its original clock
source.
Fix/Workaround:
Power-On-Reset can be used to resume back to original clock
if clock failure has occurred.
4.If the Peripheral Touch Controller
(PTC) is enabled in sleep mode, the PTC might stop working.
Description:
If the Peripheral Touch Controller (PTC) is enabled in
sleep mode, the PTC might stop working.
Fix/Workaround:
Use QTouch Library
version 5.0.8 or later.
OR
Disable the PTC before entering sleep mode.
5.Reduced ADC accuracy for Vdd from 2.7V to 4.1V.
Description:
DNL less than -1
(missing codes) can be observed for ADC codes 256, 512 and
768.
Increased gain
error.
Fix/Workaround:
Use Vdd below 2.7V or above 4.1V if accurate ADC
is needed.