The Timer/Counter (TCNTn), Output Compare Registers (OCRA/B), and Input Capture Register (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in section Accessing 16-bit Timer/Counter Registers.

The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the block diagram) signals are all visible in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin. The clock select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkTn).

The double buffered Output Compare Registers (OCRnA/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B). See Output Compare Units. The compare match event will also set the Compare Match Flag (OCFnA/B), which can be used to generate an output compare interrupt request.

The input capture register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn) or on the analog comparator pins. The input capture unit includes a digital filtering unit (Noise canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCRnA register, the ICRn register, or by a set of fixed values. When using OCRnA as TOP value in a PWM mode, the OCRnA register cannot be used for generating a PWM output. However, the TOP value will, in this case, be double buffered allowing the TOP value to be changed in runtime. If a fixed TOP value is required, the ICRn register can be used as an alternative, freeing the OCRnA to be used as PWM output.