EEPROM Control Register

Name:
EECR
Offset:
0x3F [ID-000004d0]
Reset:
0x00
Access:
 Bit7 6 5 4 3 2 1 0 EEPM[1:0] EERIE EEMPE EEPE EERE Access R/W R/W R/W R/W R/W R/W Reset x x 0 0 x 0

Bits 5:4 – EEPM[1:0]: EEPROM Programming Mode Bits

EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the erase and write operations into two different operations. The programming times for the different modes are shown in the table below. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 1. EEPROM Mode Bits
EEPM[1:0] Typ. Programming Time Operation
00 3.4ms Erase and Write in one operation (Atomic Operation)
01 1.8ms Erase Only
10 1.8ms Write Only
11 - Reserved for future use

Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to '1' enables the EEPROM ready interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM ready interrupt generates a constant interrupt when EEPE is cleared. The interrupt will not be generated during EEPROM write or SPM.

Bit 2 – EEMPE: EEPROM Master Write Enable

EEPROM Master Write Enable

The EEMPE bit determines whether writing EEPE to '1' causes the EEPROM to be written.

When EEMPE is '1', setting EEPE within four clock cycles will write data to the EEPROM at the selected address.

If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to '1' by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.

Bit 1 – EEPE: EEPROM Write Enable

EEPROM Write Enable

The EEPROM write enable signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to '1' to write the value into the EEPROM. The EEMPE bit must be written to '1' before EEPE is written to '1', otherwise, no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):
1. 1.Wait until EEPE becomes zero.
2. 2.Wait until SPMEN in SPMCSR becomes zero.
3. 3.Write new EEPROM address to EEAR (optional).
4. 4.Write new EEPROM data to EEDR (optional).
5. 5.Write a '1' to the EEMPE bit while writing a zero to EEPE in EECR.
6. 6.Within four clock cycles after setting EEMPE, write a '1' to EEPE.

The EEPROM cannot be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted.

CAUTION:

An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

Bit 0 – EERE: EEPROM Read Enable

The EEPROM read enable signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a '1' to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register.

The calibrated oscillator is used to time the EEPROM accesses. See the following table for typical programming times for EEPROM access from the CPU.

Table 2. EEPROM Programming Time
Symbol Number of Calibrated RC Oscillator Cycles Typ. Programming Time
EEPROM write (from CPU) 26,368 3.3ms

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example(1)
EEPROM_write:
; Wait for completion of previous write
sbic     EECR,EEPE
rjmp     EEPROM_write
out     EEARH, r18
out     EEARL, r17
; Write data (r16) to Data Register
out     EEDR,r16
; Write logical one to EEMPE
sbi     EECR,EEMPE
; Start eeprom write by setting EEPE
sbi     EECR,EEPE
ret
C Code Example(1)
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address and Data Registers */
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
Note: (1) Refer to About Code Examples

The following code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example(1)

EEPROM_read:
; Wait for completion of previous write
sbic     EECR,EEPE
out     EEARH, r18
out     EEARL, r17
; Start eeprom read by writing EERE
sbi     EECR,EERE
; Read data from Data Register
in      r16,EEDR
ret

C Code Example(1)

unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
}