Allows data to be copied from the SPI Flash to MSS memory. The SPI SCK frequency is specified by a user-defined option allowing for a maximum SCK frequency of 80 MHz. A SPI Flash memory address and MSS destination address are specified using the mailbox.
System Service Descriptor Bit Field | Value | Description |
---|---|---|
15:7 | MBOXADDR[10:2] | For the mailbox format, see Table 2. |
6:0 | 50H | SPI Copy Service command |
The following table lists the SPI Copy Service mailbox format.
Offset | Length (bytes) | Parameter | Direction | Description |
---|---|---|---|---|
0 | 8 | DSTADDR | Input | MSS Destination address |
8 | 4 | SRCADDR | Input | SPI Flash address |
12 | 4 | NBYTES | Input | Number of bytes to transfer |
16 | 1 | OPTIONS | Input | OPTIONS (See Table 3) |
OPTIONS | Name | Description |
---|---|---|
1:0 | CLKDIV | SPI clock divider configuration. Following are the Clock Dividers and their Frequency
|
7:2 | RESERVED | Reserved |