Fetches non-volatile states of user security locks. The following table lists the description of returned LOCKS array.
| System Service Descriptor Bit Field | Value | Description |
|---|---|---|
| 15:7 | MBOXADDR[10:2] | Mailbox address. See Table 2. |
| 6:0 | 05H | Query Security service command |
The following table lists the Query Security Service mailbox format.
| Offset | Length (bytes) | Parameter | Direction | Description |
|---|---|---|---|---|
| 0 | 9 (For PolarFire® FPGA only) | Locks | Output | Lock Array |
| 33 (For PolarFire SoC FPGA only) |
| Byte | Bit | Lock | Description |
|---|---|---|---|
| 0 | 0 | UL_DEBUG | Debug instructions disable |
| 0 | 1 | UL_SNVM_DEBUG | sNVM debug disable |
| 0 | 2 | UL_LIVEPROBE | Live probes disable |
| 0 | 3 | UL_UJTAG | User JTAG interface disable |
| 0 | 4 | UL_JTAG_BS | JTAG boundary scan disable |
| 0 | 5 | UL_TVS_MONITOR | External access to System TVS monitor disable |
| 0 | 6 | UL_JTAG_MONITOR | JTAG fabric monitor enable |
| 0 | 7 | UL_JTAG | JTAG TAP disable |
| 1 | 0 | UL_PLAINTEXT | Plaintext passcode unlock disable |
| 1 | 1 | UL_FAB_PROTECT | Fabric erase/write disable |
| 1 | 2 | UL_EXT_DIGEST | External digest check disable |
| 1 | 3 | UL_VERSION | Replay protection enable |
| 1 | 4 | UL_FACT_UNLOCK | Factory test disable |
| 1 | 5 | UL_IAP | IAP disable |
| 1 | 6 | UL_EXT_ZEROIZE | External zeroization disable |
| 1 | 7 | UL_SPI_SLAVE | SPI port disable |
| 2 | 0 | UL_USL | UFS UL segment protect |
| 2 | 1 | UL_BS_AUTHENTICATE | External bitstream authentication disable |
| 2 | 2 | UL_BS_PROGRAM | External bitstream program mode disable |
| 2 | 3 | UL_BS_VERIFY | External bitstream verify mode disable |
| 2 | 4 | UL_BITS_KEYMD[0] | Bitstream key mode disable |
| 2 | 5 | UL_BITS_KEYMD[1] | Bitstream key mode disable |
| 2 | 6 | UL_BITS_KEYMD[2] | Bitstream key mode disable |
| 2 | 7 | UL_BITS_KEYMD[3] | Bitstream key mode disable |
| 3 | 0 | UL_BITS_KEYMD[4] | Bitstream key mode disable |
| 3 | 1 | UL_BITS_KEYMD[5] | Bitstream key mode disable |
| 3 | 2 | UL_BITS_KEYMD[6] | Bitstream key mode disable |
| 3 | 3 | UL_BITS_KEYMD[7] | Bitstream key mode disable |
| 3 | 4 | UL_BITS_KEYMD[8] | Bitstream key mode disable |
| 3 | 5 | UL_BITS_KEYMD[9] | Bitstream key mode disable |
| 3 | 6 | UL_BITS_KEYMD[10] | Bitstream key mode disable |
| 3 | 7 | UL_BITS_KEYMD[11] | Bitstream key mode disable |
| 4 | 0 | UL_BITS_KEYMD[12] | Bitstream key mode disable |
| 4 | 1 | UL_BITS_KEYMD[13] | Bitstream key mode disable |
| 4 | 2 | UL_BITS_KEYMD[14] | Bitstream key mode disable |
| 4 | 3 | UL_BITS_KEYMD[15] | Bitstream key mode disable |
| 4 | 4 | UL_KEYMD[0] | Global key mode disable |
| 4 | 5 | UL_KEYMD[1] | Global key mode disable |
| 4 | 6 | UL_KEYMD[2] | Global key mode disable |
| 4 | 7 | UL_KEYMD[3] | Global key mode disable |
| 5 | 0 | UL_KEYMD[4] | Global key mode disable |
| 5 | 1 | UL_KEYMD[5] | Global key mode disable |
| 5 | 2 | UL_KEYMD[6] | Global key mode disable |
| 5 | 3 | UL_KEYMD[7] | Global key mode disable |
| 5 | 4 | UL_KEYMD[8] | Global key mode disable |
| 5 | 5 | UL_KEYMD[9] | Global key mode disable |
| 5 | 6 | UL_KEYMD[10] | Global key mode disable |
| 5 | 7 | UL_KEYMD[11] | Global key mode disable |
| 6 | 0 | UL_KEYMD[12] | Global key mode disable |
| 6 | 1 | UL_KEYMD[13] | Global key mode disable |
| 6 | 2 | UL_KEYMD[14] | Global key mode disable |
| 6 | 3 | UL_KEYMD[15] | Global key mode disable |
| 6 | 4 | UL_SNVM_PROTECT | sNVM bitstream write protection enable |
| 6 | 5 | UL_EXT_CHALLENGE | CHALLENGE instruction disable |
| 6 | 6 | UL_UEK_PROTECT | UEK overwrite protection |
| 6 | 7 | UL_HWM | High Water Mark Reset disable (For PolarFire SoC FPGA only) |
| 7 | 0 | UL_ENVM_PROTECT | Disable bitstream programming of eNVM (For PolarFire SoC FPGA only) |
| 7 | 1 | UL_USER_KEY | User Key1 write protect |
| 7 | 2 | UL_USER_KEY2 | User Key2 write protect |
| 7 | 3 | UP_FACTORY | Permanent factory test disable |
| 7 | 4 | UP_DEBUG | Permanent debug disable |
| 7 | 5 | UP_FABRIC | Permanent fabric write protect |
| 7 | 6 | UP_UPK1 | Permanent disable of UPK1 |
| 7 | 7 | UP_UPK2 | Permanent disable of UPK2 |
| 8 | 0 | UP_DPK | Permanent disable of DPK |
| 8 | 1 | UP_PROTECT | Write disable for UPERM segment |
| 9:11 | — |
RESERVED | Reserved |
| 12 | 0 | UATHENA_ENA | User F5200 enable (For PolarFire® SoC FPGA only) |
| 12 | 1:2 | UATHENA_MODE | User F5200 mode (For PolarFire SoC FPGA only) |
| 12 | 3:5 | U_CLKMON_FREQ | System Controller Clock Frequency monitor configuration (For PolarFire SoC FPGA only) |
| 13 | — |
RESERVED | Reserved |
| 14-15 | — |
PORDIGEST[15:0] | This field specifies a mask of device digests that should be checked upon each power-up of the user design (For PolarFire SoC FPGA only) |
| 16-31 | — |
HWM | High Water Mark value (For PolarFire SoC FPGA only) All 1s are returned if the HWM is invalid. |
| 32 | — |
PORDIGEST[23:16] | This field specifies a mask of device digests that should be checked upon each power-up of the user design (For PolarFire SoC FPGA only) |