Start, Reset and Stop Hardware Limit Timing

The UTMR module consists of an External Reset Signal (ERS) source that can be used to Start, Reset and/or Stop the timer without any software intervention. The different Start, Reset and Stop conditions are listed in the tables below. The EPOL bit controls the polarity of the ERS signal and changes how the Start, Reset, and Stop conditions are handled in the hardware.
Table 1. Start Conditions
Start Condition Operation when EPOL = 0 Operation when EPOL = 1
None No hardware control – timer runs when ON = 1 Same as EPOL = 0
Either ERS Edge Timer starts at either edge (rising or falling) of ERS Same as EPOL = 0
Rising ERS Edge Timer starts at rising edge of ERS Timer starts at falling edge of ERS
ERS Level-1 Timer starts at the first clock where ERS has a high level and the Start condition remains asserted as long as the subsequent clocks register a high ERS level. Timer starts at the first clock where ERS has a low level and the Start condition remains asserted as long as the subsequent clocks register a low ERS level.
Table 2. Reset Conditions
Reset Condition Operation when EPOL = 0 Operation when EPOL = 1
None No hardware reset Same as EPOL = 0
ERS Level-0 + PR Match

Timer resets at the first clock where ERS has a low level and the Reset condition remains asserted as long as the subsequent clocks register a low ERS level. Level output and RUN bit become false while the Reset condition is active.

A PR match condition also triggers a Reset, in which case the timer resets at the next clock after PR match. Level output and RUN bit remain true in this case.

Timer resets at the first clock where ERS has a high level and the Reset condition remains asserted as long as the subsequent clocks register a high ERS level. Level output and RUN bit become false while the Reset condition is active.

A PR match condition also triggers a Reset, in which case the timer resets at the next clock after PR match. Level output and RUN bit remain true in this case.
At Start + PR Match Timer resets at the first clock whenever a Start condition is generated. A PR match condition also triggers a Reset, in which case the timer resets at the next clock after PR match. Level output and RUN bit remain true in either case. Same as EPOL = 0
At PR Match Timer resets at the next clock after a PR match condition is generated. Level output and RUN bit remain true in this case. Same as EPOL = 0
Table 3. Stop Conditions
Reset Condition Operation when EPOL = 0 Operation when EPOL = 1
None No hardware control – timer stops when ON = 0. Capture occurs at every rising ERS edge. No hardware control – timer stops when ON = 0. Capture occurs at every falling ERS edge.
Either ERS Edge Timer stops at either edge (rising or falling) of ERS and causes a capture event Same as EPOL = 0
Rising ERS Edge Timer stops at rising edge of ERS and causes a capture event. Timer stops at falling edge of ERS and causes a capture event
At PR Match Timer stops at the next clock after a PR match condition occurs and causes a capture event. Same as EPOL = 0
Parent topic: Basic Operation