CHANNELn

Channel Generator Selection

The specific generator name corresponding to each bit group configuration is given by combining Peripheral and Output from the table below in the following way: PERIPHERAL_OUTPUT.

GENERATOR			Async/Sync	Description	Channel Availability
Value	Name
Value	Peripheral	Output
0x01	UPDI	SYNCH	Sync	Rising edge of SYNCH character detection	All channels
0x06	RTC	OVF	Async	Counter overflow	All channels
0x07		CMP		Compare match	All channels
0x08		PIT_DIV8192		Prescaled RTC clock divided by 8192	Even numbered channels only
0x09		PIT_DIV4096		Prescaled RTC clock divided by 4096
0x0A		PIT_DIV2048		Prescaled RTC clock divided by 2048
0x0B		PIT_DIV1024		Prescaled RTC clock divided by 1024
0x08		PIT_DIV512		Prescaled RTC clock divided by 512	Odd numbered channels only
0x09		PIT_DIV256		Prescaled RTC clock divided by 256
0x0A		PIT_DIV128		Prescaled RTC clock divided by 128
0x0B		PIT_DIV64		Prescaled RTC clock divided by 64
0x10	CCL	LUT0	Async	LUT output level	All channels
0x11		LUT1
0x12		LUT2
0x13		LUT3
0x14		LUT4⁽¹⁾
0x15		LUT5⁽¹⁾
0x20	AC0	OUT	Async	Comparator output level	All channels
0x21	AC1
0x22	AC2
0x24	ADC0	RESRDY	Sync	Result ready	All channels
0x28	PTC	RESRDY	Sync	Result ready	All channels
0x30	ZCD0	OUT	Async	ZCD output level	All channels
0x31	ZCD1⁽¹⁾	OUT	Async	ZCD output level	All channels
0x40-0x47	PORTA	PIN0-PIN7	Async	Pin level⁽²⁾	CHANNEL0 and CHANNEL1 only
0x48-0x4F	PORTB⁽¹⁾	PIN0-PIN7	Async	Pin level⁽²⁾	CHANNEL0 and CHANNEL1 only
0x40-0x47	PORTC	PIN0-PIN7	Async	PIN level⁽²⁾	CHANNEL2 and CHANNEL3 only
0x48-0x4F	PORTD	PIN0-PIN7	Async	PIN level⁽²⁾	CHANNEL2 and CHANNEL3 only
0x40-0x47	PORTE ⁽¹⁾	PIN0-PIN7	Async	Pin level ⁽²⁾	CHANNEL4 and CHANNEL5 only
0x48-0x4F	PORTF	PIN0-PIN7	Async	Pin level ⁽²⁾	CHANNEL4 and CHANNEL5 only
0x60	USART0	XCK	Sync	Clock signal in SPI Host mode and synchronous USART Host mode	All channels
0x61	USART1
0x62	USART2
0x63	USART3⁽¹⁾
0x64	USART4⁽¹⁾
0x68	SPI0	SCK	Sync	SPI host clock signal	All channels
0x69	SPI1	SCK	Sync	SPI host clock signal	All channels
0x80	TCA0	OVF_LUNF	Sync	Overflow/Low byte timer underflow	All channels
0x81		HUNF	Sync	High byte timer underflow
0x84		CMP0_LCMP0	Sync	Compare channel 0 match/Low byte timer compare channel 0 match
0x85		CMP1_LCMP1	Sync	Compare channel 1 match/Low byte timer compare channel 1 match
0x86		CMP2_LCMP2	Sync	Compare channel 2 match/Low byte timer compare channel 2 match
0x88	TCA1⁽¹⁾	OVF_LUNF	Sync	Overflow/Low byte timer underflow	All channels
0x89		HUNF		High byte timer underflow
0x8C		CMP0_LCMP0		Compare channel 0 match/Low byte timer compare channel 0 match
0x8D		CMP1_LCMP1		Compare channel 1 match/Low byte timer compare channel 1 match
0x8E		CMP2_LCMP2		Compare channel 2 match/Low byte timer compare channel 2 match
0xA0	TCB0	CAPT	Sync	CAPT Interrupt flag set⁽³⁾	All channels
0xA1	TCB0	OVF	Sync	Counter overflow	All channels
0xA2	TCB1	CAPT	Sync	CAPT Interrupt flag set⁽³⁾	All channels
0xA3	TCB1	OVF	Sync	Counter overflow	All channels
0xA4	TCB2	CAPT	Sync	CAPT interrupt flag set⁽³⁾	All channels
0xA5	TCB2	OVF	Sync	Counter overflow	All channels
0xA6	TCB3⁽¹⁾	CAPT	Sync	CAPT interrupt flag set⁽³⁾	All channels
0xA7	TCB3⁽¹⁾	OVF	Sync	Counter overflow	All channels
0xB0	TCD0	CMPBCLR	Async	Counter matches CMPBCLR	All channels
0xB1		CMPASET		Counter matches CMPASET
0xB2		CMPBSET		Counter matches CMPBSET
0xB3		PROGEV		Programmable event output

Notes:

1.Not all peripheral instances are available for all pin counts. Refer to the Peripherals and Architecture section for details.
2.Event from PORT pin will be zero if the input driver is disabled.
3.The operational mode of the timer decides when the CAPT flag is raised. See the 16-bit Timer/Counter Type B (TCB) section for details.

Bit7	6	5	4	3	2	1	0
CHANNELn[7:0]
AccessR/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset0	0	0	0	0	0	0	0

Bits 7:0 – CHANNELn: Channel Generator Selection