Phase-Locked Loop (PLL)

The PLL can be used to increase the frequency of the clock source defined by the SOURCE bit in the CLKCTRL.PLLCTRLA register. The PLL provides clock multiplication by 2x or 3x, and it can be used only when the reference clock (EXTCLK or OSCHF) is at least 16 MHz.

The PLL can run in Active, Idle and Standby sleep modes and can serve as an input clock for TCD.

The maximum frequency generated using the PLL is 48 MHz.

Initialization:

1.Enable the clock source to be used as input.
2.Configure the SOURCE bit in the CLKCTRL.PLLCTRLA register to the desired clock source.
3.Enable the PLL by writing the desired multiplication factor to the MULFAC bit field in CLKCTRL.PLLCTRLA.
4.Wait for the PLL Status (PLLS) bit in the CLKCTRL.MCLKSTATUS register to become ‘1’, indicating that the PLL has locked in on the desired frequency.

For available connections, refer to Block Diagram - CLKCTRL.