Writing a ‘1’ to this bit enables the interrupt which indicates that the EEPROM is ready for new write/erase operations.

This is a level interrupt that will be triggered only when the EEREADY bit in the INTFLAGS register is set to ‘1’. The interrupt must not be enabled before triggering an EEPROM write/erase operation, as the EEREADY bit will not be cleared before this command is issued. The interrupt must be disabled in the interrupt handler.