LUT n Control A

Name:
LUTnCTRLA
Offset:
0x08 + n*0x04 [n=0..5]
Reset:
0x00
Access:
Enable-Protected
Bit76543210
EDGEDETOUTENFILTSEL[1:0]CLKSRC[2:0]ENABLE
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000

Bit 7 – EDGEDET: Edge Detection

Edge Detection

ValueDescription
0 Edge detector is disabled
1 Edge detector is enabled

Bit 6 – OUTEN: Output Enable

Output Enable

This bit enables the LUT output to the LUTn OUT pin. When written to ‘1’, the pin configuration of the PORT I/O-Controller is overridden.
ValueDescription
0 Output to pin disabled
1 Output to pin enabled

Bits 5:4 – FILTSEL[1:0]: Filter Selection

Filter Selection

These bits select the LUT output filter options.

ValueNameDescription
0x0 DISABLE Filter disabled
0x1 SYNCH Synchronizer enabled
0x2 FILTER Filter enabled
0x3 - Reserved

Bits 3:1 – CLKSRC[2:0]: Clock Source Selection

Clock Source Selection

This bit selects between various clock sources to be used as the clock (CLK_LUTn) for an LUT.

The CLK_LUTn of the even LUT is used for clocking the sequencer of an LUT pair.

Value Input Source Description
0x0 CLKPER CLK_PER is clocking the LUT
0x1 LUTn-TRUTHSEL[2] LUTn-TRUTHSEL[2] is clocking the LUTn
0x2 - Reserved
0x3 - Reserved
0x4 OSCHF Internal high-frequency oscillator before prescaler is clocking LUT
0x5 OSC32K Internal 32.786 kHz oscillator
0x6 OSC1K Internal 32.768 kHz oscillator divided by 32
0x07 - Reserved

Bit 0 – ENABLE: LUT Enable

LUT Enable

ValueDescription
0 The LUT is disabled
1 The LUT is enabled