This flag is set to ‘1’ when the client byte transmit or receive operation is completed without any bus errors. This flag can be set to ‘1’ with an unsuccessful transaction in case of a collision detection. More information can be found in the Collision (COLL) bit description.

The DIF flag can generate a client data interrupt. More information can be found in Data Interrupt Enable (DIEN) bit from the Client Control A (TWIn.SCTRLA) register.

This flag is automatically cleared when accessing several other TWI registers. The DIF flag can be cleared by choosing one of the following methods:

1. 1.Writing/Reading the Client Data (TWIn.SDATA) register.
2. 2.Writing to the Command (SCMD) bit field from the Client Control B (TWIn.SCTRLB) register.

This flag is set to ‘1’ when the client address has been received or by a Stop condition.

The APIF flag can generate a client address or stop interrupt. More information can be found in the Address or Stop Interrupt Enable (APIEN) bit from the Client Control A (TWIn.SCTRLA) register.

This flag can be cleared by choosing one of the methods described for the DIF flag.

When this bit is read as ‘1’, it indicates that the client is currently holding the SCL low, stretching the TWI clock period.

This bit is set to ‘1’ when an address or data interrupt occurs. Resetting the corresponding interrupt will indirectly set this bit to ‘0’.

When this flag is read as ‘0’, it indicates that the most recent Acknowledge bit from the host was ACK.

When this flag is read as ‘1’, it indicates that the most recent Acknowledge bit from the host was NACK.

Writing a ‘1’ to this bit will clear the COLL flag. The flag is automatically cleared if any Start condition (S/Sr) is detected.

The BUSERR flag indicates that an illegal bus operation has occurred. Illegal bus operation is detected if a protocol violating the Start (S), repeated Start (Sr), or Stop (P) conditions is detected on the TWI bus lines. A Start condition directly followed by a Stop condition is one example of a protocol violation. Writing a ‘1’ to this bit will clear the BUSERR flag.

The TWI bus error detector is part of the TWI host circuitry. For the bus errors to be detected by the client, the TWI Dual mode or the TWI host must be enabled, and the main clock frequency must be at least four times the SCL frequency. The TWI Dual mode can be enabled by writing ‘1’ to the ENABLE bit in the TWIn.DUALCTRL register. The TWI host can be enabled by writing ‘1’ to the ENABLE bit in the TWIn.MCTRLA register.

This bit indicates the current TWI bus direction. The DIR bit reflects the direction bit value from the last address packet received from a host TWI device.

When this bit is read as ‘1’, it indicates that a host read operation is in progress.

When this bit is read as ‘0’, it indicates that a host write operation is in progress.

When the TWI client Address or Stop Interrupt Flag (APIF) is set to ‘1’, this bit determines whether the interrupt is due to an address detection or a Stop condition.