Three different sleep modes can be enabled to reduce power consumption.
| Idle
| The CPU stops executing code, resulting in reduced power consumption.
All peripherals are running, and all interrupt sources can wake the device.
|
| Standby
| All high-frequency clocks are stopped unless running in Standby sleep mode is
enabled for a peripheral or clock. This is enabled by writing the corresponding
RUNSTDBY bit to ‘1’. The power consumption is dependent on the
enabled functionality.
A subset of interrupt sources can wake the device(1).
|
| Power-Down
| All high-frequency clocks are stopped, resulting in a power consumption lower
than the Idle sleep mode.
When operating at temperatures above 70°C, the power consumption can be reduced
further by writing the High-Temperature Low Leakage Enable (HTLLEN) bit in the
Voltage Regulator Control (SLPCTRL.VREGCTRL) register to
‘1’.
A subset of the peripherals are running, and a subset of interrupt sources can
wake the device.(1)
|
Important: The TWI address match
and CCL wake-up sources must be disabled when High-Temperature Low Leakage Enable is
activated to avoid unpredictable behavior.
Note:
- 1.Refer to the Sleep Mode Activity tables for further information.
Refer to the Wake-up Time section for information on how the wake-up time is
affected by the different sleep modes.
Table 1. Sleep Mode Activity Overview for
Peripherals
| Peripheral |
Active in Sleep Mode |
| Idle |
Standby |
Power-Down |
| HTLLEN=0 |
HTLLEN=1 |
| CPU |
|
|
|
|
| RTC |
X |
X(1,2) |
X(2) |
X(2) |
| WDT |
X |
X |
X |
X |
| BOD |
X |
X |
X |
X |
| EVSYS |
X |
X |
X |
X |
| CCL |
X |
X(1) |
|
|
| ACn |
| ADCn |
| DACn |
| PTC |
| ZCDn |
| TCAn |
| TCBn |
| All other peripherals |
X |
|
|
|
Notes:
- 1.For the peripheral to run in Standby
sleep mode, the RUNSTDBY bit of the corresponding peripheral must be set.
- 2.In Standby sleep mode, only the RTC functionality requires the RUNSTDBY bit to be set.
In Power-Down sleep mode, only the PIT functionality is available.
Table 2. Sleep Mode Activity Overview for Clock
Sources
| Clock Source |
Active in Sleep Mode |
| Idle |
Standby |
Power-Down |
| HTLLEN=0 |
HTLLEN=1 |
| Main clock source |
X |
X(1) |
|
|
| RTC clock source |
X |
X(1,2) |
X(2) |
X(2) |
| WDT oscillator |
X |
X |
X |
X |
| BOD oscillator(3) |
X |
X |
X |
X |
| CCL clock source |
X |
X(1) |
|
|
| TCD clock source |
X |
|
|
|
Notes:
- 1.For the clock source to run in Standby
sleep mode, the RUNSTDBY bit of the corresponding peripheral must be set.
- 2.In Standby sleep mode, only the RTC
functionality requires the RUNSTDBY bit to be set. In Power-Down sleep mode, only the
PIT functionality is available.
- 3.The Sampled mode only.
Table 3. Sleep Mode Wake-up Sources
| Wake-Up Sources |
Active in Sleep Mode |
| Idle |
Standby |
Power-Down |
| HTLLEN=0 |
HTLLEN=1 |
| PORT Pin interrupt |
X |
X |
X(1) |
X(1) |
| BOD VLM interrupt |
X |
X |
X |
X |
| RTC interrupts |
X |
X(2,3) |
X(3) |
X(3) |
| TWI Address Match interrupt |
X |
X |
X |
- |
| CCL interrupts |
X |
X |
X(4) |
- |
| USART Start-Of-Frame interrupt |
- |
X |
- |
- |
| TCAn interrupts |
X |
X |
- |
- |
| TCBn interrupts |
| ACn interrupts |
| ADCn interrupts |
| PTC interrupts |
| ZCD interrupts |
| All other interrupts |
X |
- |
- |
- |
Notes:
- 1.Only fully asynchronous pins can trigger an interrupt and wake up the device from all
sleep modes, including modes where the Peripheral Clock (CLK_PER) is stopped. Refer to
the I/O Multiplexing and Considerations section for further details on which
pins support fully asynchronous pin change sensing.
- 2.For the peripheral to run in Standby
sleep mode, the RUNSTDBY bit of the corresponding peripheral must be set.
- 3.In Standby sleep mode, only the RTC
functionality requires the RUNSTDBY bit to be set. In Power-Down sleep mode, only the
PIT functionality is available.
- 4.CCL will only wake up the device if the
path through LUTn is asynchronous (FILTSEL=
0x0 and
EDGEDET=0x0 in the CCL.LUTnCTRLA register).