Sample Control
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SAMPLEN[7:0] | |||||||
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Sample Length
This bit field extends the ADC sampling time with the number of CLK_ADC cycles given by the bit field value. Increasing the sampling time allows sampling sources with higher impedance. By default, the sampling time is two CLK_ADC cycles. The total conversion time increases with the selected sampling length.